| DDR Memory Design and Test – A Better Way
Agilent offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.
手冊 2012-12-19
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 PDF 5.17 MB |
| DDR Memory Design and Test Overview
Brief overview of Agilent solutions for DDR design and test.
手冊 2012-12-19
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PDF 1.14 MB |
| E2688A 串行數(shù)據分析和時鐘恢復軟件
Agilent E2688A串行數(shù)據分析軟件為工程師提供驗證串行接口設計信號完整性的便捷方法。
產品資料 2012-06-28
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PDF 733 KB
語言
- English | 2013-01-15 | PDF 6.07 MB
- 中文（簡體） | 2012-06-28 | PDF 733 KB
- 日本語 | 2005-07-01 | PDF 728 KB
- 中文（繁體） | 2004-10-04 | PDF 855 KB
- ??? | 2003-10-03 | PDF 988 KB
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| U7231A DDR3 Compliance Test Application for Infiniium Series Oscilloscopes
The Agilent Technologies U7231A DDR3 compliance test application provides a fast and easy way to test, debug and characterize your DDR3 designs.
產品資料 2011-12-13
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PDF 1.23 MB
語言
- English | 2011-12-13 | PDF 1.23 MB
- 日本語 | 2008-06-27 | PDF 8.54 MB
- 中文（繁體） | 2009-09-01 | PDF 1.34 MB
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| U7231A DDR3 Compliance Test Application Testing Notes
Describes the tests that are performed by the DDR3 Compliance Test Application in more detail.
用戶手冊 2011-03-01
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PDF 6.01 MB |
| Agilent W2630 系列 DDR2 DRAM BGA 探頭安裝指南
Agilent W2630 系列 DDR2 DRAM BGA 探頭安裝指南
產品資料 2009-10-08
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PDF 971 KB
語言
- English | 2009-10-08 | PDF 971 KB
- 中文（簡體） | 2009-10-08 | PDF 971 KB
- 日本語 | 2009-06-23 | PDF 1.69 MB
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| U7231A DDR3 Compliance Test Application Online Help
This is a zipped Microsoft Windows® format help file. Extract this file to a Local Disk (a Windows security requirement); on Windows XP, you may have to open the file's Properties dialog and Unblock the file before opening.
幫助文件 2009-07-01
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 ZIP 2.40 MB |
| Eye-Diagram Analysis Speeds DDR SDRAM Validation
文章 2009-01-06
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| Validating the Physical and Protocol Layers in DDR Memory Interfaces
文章 2009-01-06
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| 適用于 Infiniium 90000 和 8000 系列示波器的 Agilent InfiniiScan 事件識別軟件
InfiniiScan 軟件能讓您用示波器識別電子設計的信號完整性問題
產品資料 2008-10-20
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PDF 783 KB
語言
- English | 2009-12-12 | PDF 1017 KB
- 中文（簡體） | 2008-10-20 | PDF 783 KB
- 日本語 | 2009-07-07 | PDF 2.42 MB
- ??? | 2006-02-07 | PDF 823 KB
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| A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate synchronous dynamic random access memory) signals.
應用說明 2008-09-10
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PDF 792 KB
語言
- English | 2008-09-10 | PDF 792 KB
- 日本語 | 2007-07-24 | PDF 4.08 MB
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| Simplify DDR Validation with SI Methods
文章 2008-01-06
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| DDR 1, 2 and 3 solutions Video
Includes probing methods, read/write separation technique and automated JEDEC compliance measurements with Infiniium Series oscilloscopes.
基本演示 2007-12-27
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 WMF 52.75 KB |
| Infiniium 80000B Series Oscilloscopes and InfiniiMax Series Probes
Infiniium 80000B Series scopes and InfiniiMax probing system include the industry’s lowest noise floor, lowest jitter measurement floor, lowest trigger jitter and flattest
產品資料 2007-12-06
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PDF 1.25 MB |
| 改善查看周期:調試DDR和DD2系統(tǒng)中的間歇
應用說明 2006-05-01
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PDF 5.93 MB
語言
- English | 2006-04-14 | PDF 120 KB
- 中文（簡體） | 2006-05-01 | PDF 5.93 MB
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| Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...
應用說明 2001-12-20
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PDF 1.51 MB
語言
- English | 2001-12-20 | PDF 1.51 MB
- 日本語 | 2002-04-04 | PDF 633 KB
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